1、功能说明
    此例程展示了CM4内核下的ECCMON的基本配置方法。

2、使用环境

    软件开发环境：KEIL MDK-ARM V5.34
                 IAR EWARM 8.50.1
    芯片支持：
            N32H785
            N32H785xxxEC
            N32H787

3、使用说明

    系统配置
        1、时钟源： HSI+PLL
        2、系统时钟频率：
            M7核 600MHz  M4核 300MHz
        3、ECCMON：
            配置ECCMON2捕获AHB_SRAM5_BANK1和AHB_SRAM5_BANK2的1/2bit ECC错误
            向AHB_SRAM5_BANK1注入1bit错误测试AHB_SRAM5_BANK1
            向AHB_SRAM5_BANK2注入2bit错误测试AHB_SRAM5_BANK1

    使用方法：
        1、将78x的GPIO的LedBlink demo和当前CM4的工程程序分别编译后下载到开发板并复位运行;
        2、可观察到PA2间隔1s循环点亮指示CM4正在运行;
        3、可通过串口助手查看到如下log:
            AHB_SRAM5_BANK1 1bit read error.
            AHB_SRAM5_BANK1 1bit partial write error.
            AHB_SRAM5_BANK2 2bit read error.
            AHB_SRAM5_BANK2 2bit partial write error.

4、注意事项
    1、为了获取正确的ECC码，需要在使能ECCMON后，先初始化内存，否则不正确的ECC码会错误的产生错误标志
    2、在初始化内存过程中，会产生不可用的错误标志，需求清除
    3、当产生错误，读完addr/data/code后，需要清除E1EAD/E2EAD，否则addr/data/code寄存器被锁定，下一次错误产生，寄存器不会更新
    
1. Function description

    This example shows the basic configuration of ECCMON in the condition of CM4.

2. Development environment

    Software development environment: KEIL MDK-ARM V5.34
                                      IAR EWARM 8.50.1
    
    MCU support:
        N32H785
        N32H785xxxEC
        N32H787

3. How to use

    System Configuration:
        1. Clock source: HSI+PLL
        2. System Clock frequency: 
            M7 Core：600MHz  M4 Core：300MHz
        3.ECCMON:
            ECCMON2 capture the 1/2bits ECC error of AHB_SRAM5_BANK1/AHB_SRAM5_BANK2
            inject 1bit error to AHB_SRAM5_BANK1 for testing
            inject 2bit error to AHB_SRAM5_BANK2 for testing

     Instructions:
        1. Compile the LedBlink demo for 78x's GPIO and the current CM4 project program respectively, 
           then download them to the development board and reset to run；
        2. PA2 flashes to indicate that the M4 core is running; 
        3. by usart assistant ,get the log:
            AHB_SRAM5_BANK1 1bit read error.
            AHB_SRAM5_BANK1 1bit partial write error.
            AHB_SRAM5_BANK2 2bit read error.
            AHB_SRAM5_BANK2 2bit partial write error.

4. Attention
    1、To obtain the correct ECC code, it is necessary to initialize the memory after enabling ECCMON,
       otherwise, incorrect ECC code will wrongly generate an error flag.
    2、During the initialization of memory, an unavailable error flag will be generated, which needs to be cleared .
    3、When an error occurs,After reading addr/data/code, E1EAD/E2EAD need to be cleared; otherwise,
      the addr/data/code register will be locked and will not be updated the next time an error occurs

