1、功能说明

    此例程提供了SPI 读、写、擦除片外FLASH。  

2、使用环境

    软件开发环境：KEIL MDK-ARM V5.34.0.0
    硬件开发环境： 
        N32G05x系列：
            基于评估板N32G05xRBQ7_STB V1.0开发
        N32G05x系列：
            基于评估板N32G05xRBL7_STB V1.0开发
    片外FLASH：GD25Q16

3、使用说明
	
    1、时钟源：HSE+PLL
    2、主时钟：64MHz
    3、SPI1 配置：
            SCK   -->  PB12
            MISO  -->  PB11
            MOSI  -->  PB10
            CS    -->  PB9
            全双工
            主模式
            8bit传输
            极性：起始为低/第二个边沿
            软件片选
            大端在前MSB

    4、使用方法：
          1、编译后下载程序复位运行；
           2、通过 SPI1 读取 GD25Q16 的 ID，然后写数据，再读出来，比较读写数据，查看 TransferStatus1 状态为 PASSED，然后擦除块，检查擦除块正常。

4、注意事项
    1. 需根据主机时钟空闲电平来配置主机CLK引脚的上/下拉，CLKPOL为1配置为上拉，CLKPOL为0配置为下拉.


1. Function description
    This routine provides SPI for reading, writing, and erasing off chip FLASH.

    
2. Use environment
	Software development environment: KEIL MDK-ARM V5.34.0.0
    Hardware development environment:
         N32G05x series:
            Developed based on the evaluation board N32G05xRBQ7_STB V1.0
         N32G05x series:
            Developed based on the evaluation board N32G05xRBL7_STB V1.0
    Off-chip FLASH: GD25Q16
    
3. Instructions for use

	/* Describe related module configuration methods; for example: clock, I/O, etc. */
	1. SystemClock: 64MHz
    2. clock source:HSE+PLL

    3. SPI1 configuration:
        SCK   -->  PB12
        MISO  -->  PB11
        MOSI  -->  PB10
        CS    -->  PB9
    	Full duplex
    	Main mode
    	8 bit transmission
    	Polarity: start at low/second edge
    	Piece of software to choose
    	Big end in front MSB

    4.Instructions:
        1. After compiling, download the program to reset and run;
        2. Read the ID of GD25Q16 through SPI1, then write the data, then read it out, compare the read and write data, check the status of TransferStatus1 as PASSED, 
            then erase the block, and check the erase block is normal;

4. Precautions
    1. The pull-up/down of the host CLK pin should be configured according to the idle level of the host clock，
        when CLKPOL is set to 1, it is configured as pull-up; when CLKPOL is set to 0, it is configured as pull-down.
